Electronic information handling or computer systems, whether large machines, microcomputers or small and simple digital processing devices, require memory for storing data and program instructions. Various memory systems have been developed over the years to address the evolving needs of information handling systems. One such memory system includes integrated circuit memory devices.
Integrated circuit memory devices are rapidly-accessible memory devices. In an integrated circuit memory device, the time required for storing and retrieving information generally is independent of the physical location of the information within the memory device. Semiconductor memory devices typically store information in a large array of cells.
Computer, communication and industrial applications are driving the demand for memory devices in a variety of electronic systems. One important form of semiconductor memory device includes Dynamic Random Access Memory (DRAM). A typical DRAM includes an array of memory cells. Each memory cell includes a capacitor that stores the data in the cell and a transistor that controls access to the data. The charge stored across the capacitor is representative of a data bit.
Data can be either stored in the memory cells during a write mode, or data may be retrieved from the memory cells during a read mode. The data is transmitted on signal lines, referred to as bit lines, which are coupled to input/output (I/O) lines through transistors used as switching devices. Typically, for each bit of data stored, its true logic state is available on an I/O line and its complementary logic state is available on an I/O complement line.
The memory cells are typically arranged in an array and each cell has an address identifying its location in the array. The array includes a configuration of intersecting conductive lines, i.e., the bit lines and word lines. Memory cells are located at intersections of the bit lines and word lines. In order to read from or write to a cell, the particular cell in question must be selected, or addressed. The address for the selected cell is represented by input signals to an address decoder. In response to the decoded address, row access circuitry activates a word line. The selected word line activates the access transistors for each of the memory cells in communication with the selected word line. In response to the decoded column address, column access circuitry selects a bit line. For a read operation, the selected word line activates the access transistors for a given word line address, and data is latched to the selected bit line.
Designers are under constant pressure to increase memory cell density to reduce costs and increase performance. As memory cell density is increased, memory cell size is generally decreased. Available die area for the capacitor also generally decreases with decreasing memory cell size. As capacitance is proportional to capacitor surface area, decreasing the available die area makes it more difficult to maintain capacitance levels. While three-dimensional structures, enhanced surface area materials and high-k dielectric materials can be used to increase capacitance for a given die area, these techniques have practical limitations.
To read a memory cell of the type described herein, the charge stored on the capacitor is sensed and amplified. Sensing of the charge stored on the capacitor often involves sensing a differential between a reference node and a sensing node coupled to the capacitor. If the capacitance of the memory cell capacitor becomes too small, it may become difficult or impossible to sense this differential.
For the reasons stated above, and for other reasons stated below that will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative structures and processes for improving capacitance in memory devices.